IMAGE MAKING APPARATUS, AND METHOD FOR CONTROLLING AN IMAGE MAKING APPARATUS.

专利摘要:
image forming apparatus, and method for controlling an image forming apparatus. an image forming apparatus includes first and second memories, and a master controller and a slave controller. the main controller performs a control operation, using the first memory in a normal mode state, the secondary controller is mounted on an actuating unit provided in the image forming apparatus, to perform the image forming task, by actuating the actuating unit in a state normally, under the control of the main controller, the main controller transmits a low power mode change request to the secondary controller, if a condition to change a mode state, from the normal mode state to a low mode state. power, is satisfied, and the secondary controller copies a low power service program, stored in the first memory, to the second memory, if the low power mode change request is received, and performs a low power service, by running the low power service program by accessing the second memory.
公开号:BR112013025855B1
申请号:R112013025855-1
申请日:2012-05-04
公开日:2021-08-24
发明作者:Ho-beom PARK
申请人:Hewlett-Packard Development Company, L.P.；
IPC主号:

专利说明:

Technical Domain
The present disclosure generally relates to an image forming apparatus and a method for its control, and more particularly an image forming apparatus and a method for its control, which can implement a low energy mode. Fundamentals of Technique
Recently, a demand for low power consumption of all electronic devices has been gradually reinforced, and electronic devices, which do not meet such demand, even if they have an advantage in performance and price, cannot be sold due to corresponding regulatory restriction.
The current Energy Star specification requires that power consumption in a standby mode is equal to or less than 1 to 2W, depending on the type of appliance. Henceforth, even in a standby state, where a network service is possible, a power consumption equal to or less than 1W will be required, and all electronic companies have mobilized various methods to comply with this requirement.
Furthermore, it is necessary that a consumer does not experience any inconvenience depending on whether the device is in a low power state, or in a normal operating state.
According to a current method, which most companies adopt to achieve a low-power standby (standby) mode, a high-performance main CPU and a low-power auxiliary CPU are configured and, in a normal mode, a service is provided through the main CPU, whereas, if the system enters a standby mode in accordance with a specified condition, the main CPU and unnecessary system power are turned off, and the monitoring of a service request is performed through the auxiliary CPU. In this case, if a user requests a service, the auxiliary CPU applies power to the main CPU and auxiliary circuits to provide the requested service. That is, in addition to the existing CPU cores, a separate CPU having a small port size must be added.
For example, a related art system is provided with a slave controller, which is mounted on it, in addition to the master controller, to recognize IO reception processing events and activation in a low-power mode, and apply power to the master controller. In this case, since a separate chip is assembled, the price is higher, and separate circuits and software for communication between the main controller and the secondary controller are required.
As another example, CPUs of the main controller and the slave controller are integrated in one SoC, and in a service mode, the main controller controls the MAC, USB, Fax and 10 ports, while in a low power mode, the secondary controller processes data such as MAC, USB, Fax and 10 ports. Even in this case, it is necessary to add a separate CPU for low power. Disclosure of Invention Technical Problem
The present disclosure has been made to address at least the above problems and/or disadvantages, and provide at least the advantages described below. In this regard, an aspect of the present disclosure provides an image forming apparatus and a method for controlling it, which can implement a low power mode, without adding a separate CPU, Solution to Problem
In accordance with one aspect of the present disclosure, an image forming apparatus includes first and second memories; and a master controller and a slave controller; where the main controller performs a control operation, using the first memory in a normal mode state, the secondary controller is mounted on a drive unit provided in the imager apparatus to perform an image forming task, by driving the drive unit in a normal mode state under the control of the main controller, the main controller transmits a low power mode change request to the secondary controller 5, if a condition to change the mode, from the normal mode state to a low power mode state , is satisfied, and the secondary controller copies a low-power service program, stored in the first memory, to the second memory, if the low-power mode change request is received, and performs a low-power service by executing the program. low power service, through access to the second memory.
The image forming apparatus according to an embodiment of the present disclosure may further include an inter-controller communication unit for relay communication between the master controller and the slave controller; and an address change unit for setting a memory address to be accessed by the secondary controller in the low power state; where the secondary controller controls the address change unit for setting the memory address to be accessed in the second memory, and performs the low power service by running the low power service program by accessing the second memory according to the defined memory address.
The primary controller and the slave controller can be arranged in different power domains, and if low power mode is performed, the slave controller can intercept the power, which is supplied to the power domain, in which the primary controller is arranged .
The image forming apparatus, according to an embodiment of the present disclosure, may further include a power supply for supplying power to respective power domains, in which the main controller and the secondary controller are disposed, if the image forming apparatus. images is on; where, if the imager is turned on, and power is supplied, the main controller assumes a reset release state to perform initialization, sets the access address by controlling the change of address unit, transmits a reset release signal to the secondary controller and then operate in the normal mode state by starting a main program, and the secondary controller maintains a reset state, until the reset release signal is received, after the instrument imager is turned on, and if the reset release signal is received, it assumes the reset release state to operate in the normal mode state.
In accordance with another aspect of the present disclosure, an image forming apparatus includes first and second memories; and a master controller and a slave controller; where the main controller performs a control operation using the first memory in a normal mode state, the secondary controller is mounted on a drive unit provided in the imager apparatus to perform an imaging task by driving the drive unit into a state normally under the control of the main controller and to perform a low power service in a low power mode state, the main controller copies a low power service program stored in the first memory to the second memory and transmits a reset signal to the secondary controller, if a condition to change the mode state from the normal mode state to a low power mode state is satisfied, and the secondary controller performs the low power service by executing the low power service, through access to the second memory, if the reset signal is received.
The image forming apparatus according to another embodiment of the present disclosure may further include an inter-controller communication unit for relay communication between the master controller and the slave controller; and an address change unit for setting a memory address to be accessed by the secondary controller in the low power state; where the main controller controls the address change unit to set the memory address to be accessed in the second memory, and the secondary controller performs the low power service, executing the low power service program, through accessing the second memory , according to the set memory address, if the reset signal is received.
The primary controller and the slave controller can be arranged in different power domains, and if low power mode is performed, the slave controller can intercept the power, which is supplied to the power domain, in which the primary controller is arranged .
The image forming apparatus, according to an embodiment of the present disclosure, may further include a power supply for supplying power to respective power domains, in which the main controller and the secondary controller are disposed, if the image forming apparatus. images is turned on; wherein, if the imager is turned on and power is supplied, the main controller assumes a reset release state to perform initialization, sets the access address by controlling the address change unit, transmits a reset release signal to the secondary controller and then operate in the normal mode state by starting a main program, and the secondary controller maintains a reset state, until the reset release signal is received, after the forming apparatus of images is turned on, and if the reset release signal is received, it assumes the reset release state to operate in the normal mode state.
In accordance with yet another aspect of the present disclosure, an image forming apparatus includes an actuator unit performing an image forming task; a drive unit controller mounted on the drive unit to perform the imaging task; and a main controller for controlling an operation of the driver unit, communicating with the driver of the driver unit in a normal mode and being inactivated, if the imager changes the mode to a low power mode; wherein the drive unit controller performs the imaging task, by driving the drive unit in the normal mode under the control of the main controller, and provides a service that corresponds to the low power mode, if the imaging apparatus changes the mode to low power mode.
The image forming apparatus, in accordance with yet another embodiment of the present disclosure, may further include first and second memories; and a unit accessed by the secondary controller in the low power state; where the secondary controller performs a control operation using the first memory in the normal mode state, and the address change unit sets the memory address to be accessed by the secondary controller in the second memory under the control of the secondary controller, or the controller main.
The primary controller and the slave controller can be arranged in different power domains, and if low power mode is performed, the slave controller can intercept the power, which is supplied to the power domain, in which the primary controller is arranged .
The secondary controller can perform at least one of the first memory auto update mode change, a clock speed change to low power mode, a network connection speed change, and a hardware setting (H/ W) for low power mode service, when the mode is changed from normal mode to low power mode.
According to yet another aspect of the present disclosure, a method for controlling an image forming apparatus including first and second memories, a main controller performing a control operation using the first memory in a normal mode state, and a secondary controller mounted on the driver unit for performing an imaging task by driving the driver unit in the normal mode state under the control of the main controller, includes the main controller transmitting a low power mode change request to the secondary controller if a condition to change the mode state from the normal mode state to a low power mode state is satisfied; the secondary controller copying a low power service program stored in the first memory to the second memory if the low power mode change request is received; and the secondary controller providing a low power service by executing the low power service program by accessing the second memory.
In the method for controlling an image forming apparatus, according to yet another embodiment of the present disclosure, the image forming apparatus may further include an inter-controller communication unit relaying communication between the master controller and the slave controller, and a unit address change by setting a memory address to be accessed by the secondary controller in the low power state; and the method for controlling the image forming apparatus may further include the secondary controller of the second memory address change unit; wherein the provision of the low energy service provides the low energy service by executing the low energy service program by accessing the second memory in accordance with the defined memory address.
The master controller and the slave controller may be arranged in different power domains, and the method for controlling an image forming apparatus, according to yet another embodiment of the present disclosure, may further include the slave controller intercepting energy, which is supplied to the power domain, in which the main controller is disposed, if low power mode is performed.
The method for controlling an image forming apparatus, according to yet another embodiment of the present disclosure, may further include supplying power to respective power domains, in which the main controller and the secondary controller are disposed, if the imaging apparatus. of images is turned on; if the imager is turned on and power is supplied, the main controller, assuming a reset release state to perform initialization, setting the access address, through the control of the address change unit, transmits a signal of reset release to the secondary controller and, the initialization of a main program, after transmitting the reset release signal to the secondary controller; and the secondary controller maintains a reset state, until the reset release signal is received, after the imager is turned on, and if the reset release signal is received, assume the reset release state to operate in normal mode state.
According to yet another aspect of the present disclosure, a method for controlling an image forming apparatus including first and second memories, a main controller performing a control operation using the first memory in a normal mode state, and a secondary controller mounted on the drive unit for performing an imaging task, by driving the drive unit in the normal mode state under the control of the main controller, and performing a low power service in a low power mode state, includes the main controller copying a program of low power service, stored in the first memory, to the second memory, and transmitting a reset signal to the secondary controller, if a condition to change the mode state, from the normal mode state to a low power mode state , is satisfied; and the secondary controller provides the low power service by executing the low power service program by accessing the second memory if the reset signal is received.
In the method for controlling an image forming apparatus, according to yet another embodiment of the present disclosure, the image forming apparatus may further include an inter-controller communication unit relaying communication between the master controller and the slave controller, and a unit address change by setting a memory address to be accessed by the secondary controller in the low power state; and the method for controlling the image forming apparatus may further include the main controller operating for setting the memory address to be accessed in the second memory; wherein the operation of performing the low power service performs the low power service by executing the low power service program by accessing the second memory in accordance with the defined memory address.
The master controller and the slave controller may be arranged in different power domains, and the method for controlling an image forming apparatus, according to yet another embodiment of the present disclosure, may further include the slave controller intercepting energy, which is provided to the power domain, in which the main controller is disposed, if low power mode is performed.
In the method for controlling an image forming apparatus, according to yet another embodiment of the present disclosure, the image forming apparatus may further include a power unit supplying power to respective power domains, in which the main controller and the controller secondary are arranged if the image forming apparatus is turned on; and the method for controlling the image forming apparatus may further include, if the image forming apparatus is turned on and power is supplied, the main controller, assuming a reset release state to perform initialization, setting the access address through of the change address unit control by transmitting a reset release signal to the secondary controller and then operating in the normal mode state, by starting a main program, after transmitting the reset release signal to the controller secondary; and the secondary controller maintains a reset state, until the reset release signal is received, after the imager is turned on, and if the reset release signal is received, assume the reset release state to operate in normal mode state.
In accordance with yet another aspect of the present disclosure, a method for controlling an image forming apparatus, including a driver unit performing one mounted on the driver unit to perform the image forming task, and a main controller controlling an operation of the driver unit, by communicating with a drive unit controller in a normal mode and being inactivated, if the imaging apparatus changes the mode to a low power mode, the drive unit controller performing the imaging task by driving the drive unit in normal mode under the control of the main controller; and if the image forming apparatus changes the mode to low power mode, the drive unit controller provides a service corresponding to the low power mode.
In the method for controlling an image forming apparatus, according to yet another embodiment of the present disclosure, the image forming apparatus may further include first and second memories, and an address change unit defining a memory address to be accessed by the secondary controller in the low power state; and the method for controlling an image forming apparatus may further include the main controller performing a control operation using the first memory in the normal mode state; and if the imager changes the mode to low power mode by setting the memory address to be accessed by the slave controller in the second memory under the control of the slave controller or the master controller.
The master controller and the slave controller may be arranged in different power domains, and the method for controlling an image forming apparatus, according to yet another embodiment of the present disclosure, may further include the slave controller intercepting energy, which is supplied to the power domain, in which the main controller is disposed, if low power mode is performed.
The method for controlling an image forming apparatus, according to yet another embodiment of the present disclosure, may further include the secondary controller performing at least one of first memory's automatic update mode change, a clock speed change for low power mode, a network connection speed change, and a hardware (H/W) setting for the low power mode service when the mode is changed from normal mode to low power mode.
Therefore, the secondary controller (or secondary CPU), which was used to control the scan/drive unit/fax in a normal mode, can be used for low power service. Advantageous Effects of the Invention
As described above, according to the present disclosure, a CPU is used for real-time service in normal mode, and is used for low power service in low power mode, and thus the number of port counters of the ASIC can be reduced to improve cost competitiveness. Brief Description of Drawings
The above aspects, features and advantages and more of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram illustrating the configuration of an apparatus Fig. 2 is a flowchart illustrating a method for initializing an image forming apparatus according to an embodiment of the present disclosure; Fig. 3 is a diagram illustrating the configuration of an address change unit, according to an embodiment of the present disclosure, and an access point; Fig. 4 is a diagram illustrating the configuration of a communication unit between controllers, in accordance with an embodiment of the present disclosure; Fig. 5 is a flowchart illustrating a method for controlling an image forming apparatus in accordance with an embodiment of the present di. Fig. 6 is a flowchart illustrating a method for controlling an image forming apparatus in accordance with another embodiment of the present disclosure; Fig. 7 is a flowchart illustrating a process of restoring in a low mode power to a normal mode in accordance with one embodiment of the present disclosure; Fig. 8 is a flowchart illustrating a method for controlling an image forming apparatus in accordance with an embodiment of the present disclosure; Fig. 9 is a flowchart illustrating a method for controlling an image forming apparatus in accordance with another embodiment of the present disclosure; and Fig. 10 is a flowchart illustrating a method for controlling an image forming apparatus in accordance with yet another embodiment of the present disclosure. Mode for the Invention
Embodiments of the present disclosure are described in detail with reference to the accompanying drawings.
Fig. 1 is a block diagram illustrating the configuration of an image forming apparatus in accordance with one embodiment of the present disclosure.
Referring to Fig. 1, an image forming apparatus 100, according to an embodiment of the disclosure, includes a data receiving unit 105, a master controller 110, a first memory 115, a slave controller 120, a second memory 125, a power supply unit 130, a functional unit 135, a trigger unit 140, a context storage unit 145, an initialization mode determining unit 150, a process control unit 155, a communication unit between controllers 160, and a change of address unit 165 .
Here, the image forming apparatus 100 can be commonly implemented as a printer, photocopier, scanner, facsimile machine, or multifunctional peripheral (MFP), wherein the functions of the devices described above are implemented in multiple ways in a single device.
The imager 100 may be implemented to include a first energy domain region PD1 and a second energy domain region PD2, which separately receive energy through different power supply lines. Here, the energy domain region means a region, which receives energy through the same energy supply line.
Here, the first energy domain region PD1 may include the main controller 110, the functional unit 135, and the driver unit 140, and the second energy domain region PD2 may include the data receiving unit 105, the first memory 115 , the second memory 125, the secondary controller 120, the context storage unit 145, the initialization mode determining unit 150, the process control unit 155, the communication between controllers unit 160, and the switching unit. address 165.
According to the imager 100, the master controller 110 and the slave controller 120 are arranged in a SoC, and the slave controller performs drive/scan/fax unit control, or the like, in a normal mode. Therefore, the secondary controller typically uses a real-time operating system. Here, scanning/drive unit/fax functions, or the like, can be performed by functional unit 135 and driver unit 140. Furthermore, in case of a service in low power mode, a mode is changed so that one service low power mode is performed under the control of the primary controller 110, and the secondary controller 120 performs the low power service.
On the other hand, the master controller 110 and the slave controller 120 can be implemented by a CPU, respectively. Therefore, the master controller 110 and the slave controller may be hereinafter referred to as a master CPU and a slave CPU, respectively.
Furthermore, in addition to the main controller 110 and the slave controller 120, the data receiving unit 105, the first memory 115, the second memory 125, the power supply unit 130, the functional unit 135, the driver unit 155, and the communication unit between controllers 160 can be implemented in a SoC together with the main controller 110 and the slave controller 120.
In addition, the main controller 110, the functional unit 135, and the driver unit 140 can be arranged in a SoC, and the data receiving unit 105, the secondary controller 120, the second memory 125, the communication unit between controllers. 160, and the change of address unit 165 can be arranged in a separate SoC. In addition, the first memory 115, the process control unit 145, the context storage unit 150, and the initialization mode determining unit 155 can be arranged outside the SoC.
In this case, the slave controller 120 can be used for another purpose in a normal mode, and can be reset when the mode is changed to a low power mode. Specifically, when the mode is changed to low power mode, the secondary controller 120 is reset, micro firmware for the low power mode service is stored in the second memory 125, and the secondary controller 120 operates to a power mode. low energy.
Next, the functioning of the respective constituent elements will be described in detail.
The data receiving unit 105 operates to perform data communication with at least one external apparatus. Here, the data receiving unit 105 can be implemented as a communication module, which interfaces with the outside, such as a network, SDIO, USB, SPI, I2C, GPIO (sensor input etc.), FAX, or similar. Furthermore, at least one external device can be, representatively, a host device, such as a PC (personal computer), or the like, and can be implemented as a user terminal device, such as a cell phone, a PDA, a USB, or similar, or an external server.
The main controller 110 controls the operation of the imaging apparatus 100 and particularly performs a control operation using the first memory 115, to be described later in the normal mode state. Specifically, if a request signal for an imager task 20 is entered into a low power state, the main controller 110 changes the mode to a normal mode, activates the first memory 115, and performs the corresponding operation using the first. memory enabled 115 .
For example, the main controller 110 can handle reception and processing tasks in the normal mode. The main controller 110 may have an embedded web server, to provide a web service, or at a higher copier class, a third party application may be installed and served. In addition, a general purpose operating system such as Linux can be installed, and in case of a popular low-speed device, a real-time operating system can be installed, and the main controller 110 can directly control the scanning. / drive unit / fax, or 10 similar.
In particular, when the mode is changed from normal mode to low power mode, the main controller 110 copies context information to a context storage unit 145, and when mode 15 is changed from low power mode to mode normal, it can be started, using the context information stored in the context storage unit 145. Here, the context information can be CPU context information, which is lost when powering the first power domain region PD1 is intercepted.
Furthermore, context information of other constituent elements, which is lost when the feed of the first energy domain region PD1 is intercepted, can be included in it.
The secondary controller 120 can perform a control operation, using the second memory 125 in the low power state, and can operate the driver unit 140 to perform an image forming task under the control of the main controller 110 in the normal mode state.
Specifically, the secondary controller 120 performs a service for parts that require real-time control, such as driver/scan/fax unit controls, or the like, in normal mode. Since such a service requires real-time operation, control is done using a real-time operating system.
When the imager enters the low energy mode, the secondary controller 120 can perform an operation, in accordance with a predefined signal, using the second memory 125, as it maintains the low energy mode. Here, the predefined signal can be a state request signal from the imaging apparatus, through an application, or the like, which is provided on a host device (not shown) in a state, where maintaining low power mode it's possible. For example, the default signal can be a signal by a smart panel on the host device. Here, the smart panel is a panel provided on the host device to display the status of the imager apparatus and, for example, the status of the imager apparatus can be captured periodically through USB control communication. The user can capture a print state, a print paper state, a toner state, and a power on/off state of the imager on the host device through the smart panel.
On the other hand, when the imager goes into low power mode, the main controller 110 sends a low power service change request to the secondary controller 120, using the communication unit between controllers 160, and the secondary controller 120 changes the mode state to a state of possible preparation for changing to the low power mode, and informs the main controller 110 of its state. In this case, if mode change is not possible, due to a drive unit state, or the like, the slave controller 120 may notify the master controller 110 of a change impossible message.
If mode change is possible, main controller 110 resets secondary controller 120 using process control unit 155, stores a low-power performance program in second memory 125, and changes a memory access address so that the program is run in the second memory when the restore is released. After that, the reset is released, and the service in low power mode is performed. Here, memory access address change can be performed using address change unit 165, and its detailed description will be made later in the corresponding block description.
If the low power mode is initiated, the slave controller 120 turns off the first power domain PD1, changes the mode state to the low power state, converting the DRAM to an auto-update state, and performs a low power service. , that is, a wake-up event monitoring service.
Here, normal mode means a mode, in which the imager 100 performs normal operation, and the low-power mode means a mode, in which the power supply to most modules is intercepted or minimized in order to minimize the energy that is consumed when the system does not perform any operations.
In the low power mode, according to the present disclosure, in order to achieve the lowest standby power (equal to or less than 1W), a method can be used that converts main memory (usually an external DRAM ) to an auto-update state, and operates the program in an internal memory (usually an internal SRAM) , which is not in use in the SoC. For example, SRAM can be a small capacity memory of around 12 8KB. However, in some cases an SDRAM can be used, and a ROM can be used additionally in addition to SRAM or SDRAM.
The first memory 115 is the main memory, which is used in normal mode, and can be implemented through a non-volatile memory. For example, a DRAM (Dynamic RAM) can be used as the main memory. First memory 115 is volatile memory that is used when the main CPU operates, and a DRAM can be used as the first memory. In low power mode, the first memory 115 10 operates in an auto-update mode and consumes minimal power.
Furthermore, the first memory 115 belongs to the second power domain PD2 and is not turned off, even in low power mode. In this sense, by restoring the 15 CPU-related information, which are stored in the context storage unit 145, when the mode returns to normal mode, it is possible to return to the immediately previous execution mode and thus a prompt initialization becomes possible .
The second memory 125 is a memory, which exists inside the SoC, and can be used as storage of the program code and data of the secondary controller 120 in low power mode. For example, in the case of a USB, a program code for controlling the low power mode 25 may include at least one of the routine for determining whether a signal is assigned to the data receiving unit 105, a routine for performing an operation, according to a USB control signal, and a routine, which is required during activation to switch to normal mode. In this case, the second memory 125 can be implemented by at least one of SRAM (Static RAM) and one SDRAM (Synchronous Dynamic Random Access Memory). In addition, a RAMBus, a DRAM, a DDR-SDRAM, or the like, can be used as the second memory 125. For example, the second memory 125 can be implemented such that the secondary controller 120 reuses the SRAM, which is used in functional unit 235 inside the SoC, in low power mode. However, this is merely exemplary, and the second memory 125 can be configured by a memory outside the SoC, or it can be implemented using an external ROM and a minimally sized internal SRAM.
Furthermore, at least one of a ROM (read-only memory) and a flash memory can be used to store a code, which is needed to implement the low power mode.
According to an embodiment of the present disclosure, the second memory 125 may be implemented by an SRAM. In this case, SRAM can be used to copy the code, which is required, when implementing the low power mode, which is stored in a DRAM or a ROM, a flash memory, or the like.
Furthermore, the second memory 125 can be implemented by an SRAM, and can be used to execute a code, which is necessary when implementing the low power mode, which is stored in ROM, a flash memory, or the like.
Furthermore, the second memory 125 can be implemented by an SDRAM, and can be used to execute a code, which is necessary when implementing the low power mode, which is stored in ROM, a flash memory, or the like.
Furthermore, second memory 125 can be used together with first memory 115 in normal mode. That is, SRAM, which is used as a buffer (buffer) in processing an image in normal mode, can be reused as second memory 125 in low power mode.
In the following, to aid in understanding the present disclosure, resources of the respective memories will be briefly described.2 0 SRAM has the capability of holding data while power is supplied to the memory. Since SRAM does not require a periodic rewrite task, data can be retained after a write operation. SRAM is a small capacity memory, and has the inconvenience that it is expensive compared to DRAM, although its operating speed is very high. In this sense, SRAM is used in a place where high speed is needed but large capacity is not needed, such as a cache memory.
DRAM, unlike SRAM, has the characteristic that it must be continually rewritten in order to retain data. Therefore, DRAM is large-capacity memory, which is relatively slower than SRAM, and is used as main memory in most systems.
SDRAM has the characteristic that it operates in sync with a system clock. In theory, SDRAM can be in sync with the system bus speed of up to 200 MHz. Since SDRAM operates as a function of the system clock, it is anticipated that the system speed will be improved.
Power supply unit 130 supplies power to image forming apparatus 100.
Specifically, the power supply unit 130 supplies power to the first power domain region PD1 and the second power domain region PD2 in normal mode, and intercepts the power supply to the first power domain region PD1, and supplies power only to the second power domain region PD2 in low power mode.
On the other hand, in the above-described embodiment, it is exemplified that the main controller 110 and the slave controller 120 are implemented by CPUs, respectively, to control the imager 100. However, in some cases, the main CPU (not shown) and the slave CPU (not shown) can be implemented to provide a command to the master controller (not shown) and the slave controller (not shown) so that respective configurations can perform corresponding operations.
In addition, image forming apparatus 100, according to an embodiment of the present disclosure, may include a PLL unit (not shown), which generates different operating frequencies. The PLL unit (not shown) can provide the generated operating frequencies for the master controller 110, the slave controller 120, the first memory 115, and the second memory 125.
Functional unit 135 performs various functions, such as image processing, image compression, image decompression, and the like, which must be processed in drive unit 140 to perform the image forming task, such as printing, copying, scanning, and alike.
The operational module (not shown) can include several functional modules, which are not included in the functional unit 135, due to the capacity limitations of the functional unit 135. The operational module (not shown) can include at least one functional module, and the corresponding functional modules can be implemented on a single chip.
The functional unit 135 and the driver unit 140 are positioned in the first power domain PD1 together with the main controller 110, and in the case where no operation is required, such as in low power mode, the power supply to them is cut off by the power supply unit 130.
On the other hand, if the predefined condition is satisfied, the main controller 110 can change the mode form, from normal mode to low power mode. For example, there can be no commands for a predefined time. However, this is merely exemplary, and various mode change events can be provided.
As described above, if it is necessary to change the mode from normal mode to low power mode, the main controller 110 can copy a program to control the low power mode from the first memory 115 to an executable area of the second memory 125, or can copy a program stored in a separate ROM or flash memory to an executable area of the second memory 125. Therefore, much less capacity is needed, compared to the USB program that is stored in the first memory 115, which is used in mode normal. After code copying is completed, the power supply for the first power domain PD1 is intercepted and the appliance enters low power mode.
On the other hand, code copying can be performed such that the code, which is stored in flash memory or ROM, is copied to the DRAM to be used, or the code is copied to the SRAM to be used, when the device enters low power mode.
Slave controller 120 changes the mode from low power mode to normal mode if the default condition is met. For example, in the case of a printer, if there is an event such as panel key input, print service request, fax call or the like, the slave controller 120 can change the mode from low power mode to mode normal.
In general, the main reason for the boot time (the boot process can include a DRAM boot, a ROM to DRAM code copy, an H/W boot process, an operating system boot, and start of the service program) , when the mode returns from low-power mode to normal mode, is equal to the initial boot time, is that when the power supplied to the first power domain, where the main controller (not shown) and the DRAM (not shown) are arranged, it is cut off to change the mode to low power mode, the power supply for the main controller (not shown) and the DRAM (not shown) is cut off, and therefore the same procedure as the initial boot process runs when power is applied.
However, as described above, according to an embodiment of the present disclosure, the first memory 115, which is used in normal mode, is disposed in the second energy domain PD2, which is fed with a separate energy via a cable. power supply, which is different from the first power domain PD1, in which the main controller 110 is arranged, and the state of the first memory 115 is changed to an "auto-update" state, while the power supply for the first memory 115 is not cut, but is retained, to hold the contents of the first memory 115. Therefore, although the DRAM power is not turned off, the power consumption is reduced from 1 to 2W to 20 0mW or less to reach the Low energy consumption.
Furthermore, even if the data stored in the first memory 115 is kept, the power is reapplied to the main controller 110 after the shutdown, i.e. switching of power, of the first power domain PD1 and thus the execution context of the controller main 110 can be lost. For example, in the case where the main controller 110 is implemented by ARM, the register set and status register can be in the execution context and, in addition, defined values of IP blocks inside the SoC can be contained in it. For reference, an ARM CPU has a clock similar to the CPU for a desktop PC, but the power consumption is 40 to 450mW, which is very low compared to that of the CPU for a desktop PC.
On the other hand, according to the image forming apparatus as illustrated in Fig. 1, the main controller 110 stores the essential execution context information of the main controller 110, the functional unit 135, and the driver unit 140, which can be lost, when the power supply for the first energy domain PD is intercepted, in the context storage unit 145 of the second energy domain PD2. Therefore, restoring to the previous state, which is before the low power mode state is executed, using the context stored in the context storage unit 14 during reset, and thus it is possible to perform the quick reset.
The context storage unit 145 is a location in which information is stored, which is restored during the return to the previous state between the constituent elements belonging to the first energy domain, where information is lost, when the power supply stops. the first power domain PD1 is cut off by the power supply unit 130.
Context storage unit 145 can be a DRAM, and can be any memory, in which information is not lost, when the first power domain PD1 is off, such as NAND, NOR, SPI, SRAM, SoC internal memory, or similar. For example, the main backup information can be ARM CPU information, such as register set and status register in ARM CPU, and it can also be defined values of IP information within the SoC.
The boot mode determining unit 150 operates to determine whether boot is a normal boot mode, or a return from low power mode to normal mode. Here, the normal initialization mode means reset, when power is reapplied to the main controller 110 by the power supply unit 130. In this sense, the initialization mode determining unit 150 can be implemented by a register, which can store the information corresponding within the SoC.
If the boot mode determiner unit 150 determines that the boot mode is the low power return mode, the main controller 110 reads the register value from the boot mode determiner unit 150 prior to initialization as PLL/DDR, and performs a general boot procedure if boot mode is normal boot mode.
In addition, if the initialization mode determining unit 150 determines that the initialization mode is the low power return mode, the main controller 110 restores the register and status register for each CPU operation mode through the CPU unit. context store 145, and returns to the last realization point, to make initialization possible within several milliseconds. That is, the main controller 110 bypasses an initialization process such as PLL/DDR, releases the first memory 115 from auto-update mode, and returns directly to the previous running state (before switching to the low power state), using the information stored in the context storage unit 145.
The initialization mode determining unit 150 can be implemented to store the initialization mode using the register, and can determine the mode through an input, through an external GPIO pin, or the like. In this sense, the main controller 110 re-executes a restore vector and the subsequent process, and prevents the process from occurring in the same manner as the system power supply initialization process.
On the other hand, in case of mode shape change from low power mode to normal mode, the first memory 115 in low power mode must come out of the auto-update state. In this case, the primary controller 110 may terminate the "auto-update" mode, such as initializing the system, or the secondary controller 120 may terminate the "auto-update" mode of the first memory 115.
The process control unit 155 can carry out the control of the secondary controller 120 when the apparatus 5 enters the low power mode. Specifically, the process control unit 155 can change the mode of the first memory 115 to the auto-update mode, and control the interception of the power supply for the first power domain region PD1.
In addition, the process control unit 155 can perform initialization control of the main controller 110 and the secondary controller 120.
Specifically, the process control unit 155 controls the reset of the secondary controller 120 and 15 of the main controller 110, which is the central element that activates the changed mode in the low power state, while the secondary controller 120 performs the service in real time. (drive unit control/verification, or similar). Generally, if the CPU is in a state of 20 restore, it does not work and stops, even if power is applied to it, and if the restore is released, it reruns the operation from the initial state. In accordance with the present disclosure, using the feature described above, the secondary controller 120 is made to be in a reset state to stop execution, using the process control unit 155, when the apparatus enters the low power mode, a low power service code is mounted in the second memory 125, and the restoration is released, after the memory access address is changed, using the change address unit 165, so that the code in the second memory can be accomplished. Therefore, the secondary controller 120 can perform the low power service.
The intercontroller communication unit 160 operates to effect transmission/reception (command) of messages between the main controller 110 and the secondary controller 120.
For example, the controller-to-controller communication unit 160 can be used when the main controller 110 requests mode change (change to low power mode) from the slave controller 120, or when the slave controller 120 reports its own state to the controller. main 110.
In this case, the controller-to-controller communication unit 160 can use a message transmission method, using FIFO, and can be configured as a separate logic that can generate IRQ between controllers. As an example, the controller-to-controller communication unit 160 can be implemented using a PL390 interrupt control from ARM company.
The address change unit 165 is a logic, which changes the address issued by the slave controller 120 to a specified address. For example, in the case of an ARM CPU, the CPU jumps to a specified address (vector address) when CPU restore is released. Also, even in case an interrupt occurs, the CPU moves to the specified address. As an example, the address specified is address 0x0 or address OxffffOOOO. In this sense, in the case of the ARM CPU, an address map is formed by positioning the DRAM at address 0.
However, in low power mode, according to the present disclosure, first memory 115, which is implemented by DRAM, is not used, but second memory 125 is used. The second memory 125 is allocated with an address, which is not the address of the first memory 115, and a remapping process is needed for the CPU to use the second memory 125. That is, if an approach is made to address 0x0 , the address change unit 165 moves the address to the first memory 115 in the normal mode, and moves the address to the second memory 125 in the low power mode. In this sense, using the process control unit 155 and the address change unit 165, the secondary controller 120 is switched from the real-time processing CPU to the low-power processing CPU.
As described above, the image forming apparatus, in accordance with the present disclosure, performs a real-time task process (scan, fax, drive unit control) using a secondary controller in general mode, and performs a mode service. low standby power, that is, services such as wake event monitoring, network packet response (ARP, ICMP and device state query response), device state response using USB, and the like.
In the following, the relationship between the image forming apparatus 100, as illustrated in Fig. 1, and the host device (not illustrated) will be briefly described.
The host device (not shown) can be run representatively by a PC and, in some cases, it can be implemented in several types, such as a PDA, a PMP, a TV, and a server.
The host device (not shown) includes an application (not shown) and a host controller (not shown).
The application (not illustrated) may be software, which supports the various data communication functions in the OS (operating system).
The host controller (not shown) may be in the form of all S/W and H/W, which allow the imager apparatus 100 to be coupled to the host device 25 (not shown). The host device (not shown) may further include a printer driver (not illustrated), or the like, which converts printed data, which is prepared by an application program into a print language, which can be analyzed on the image forming apparatus 100, and can be applied in the form it is. included with the host controller (not shown).
Furthermore, the host device may include normal constituent elements of the host device (not shown), such as an input unit (not shown), a display unit (not shown) and the like.
On the other hand, the constitutive elements, as illustrated in Fig. 1, and their order of arrangement, are merely exemplary and, if necessary, part of the constitutive elements can be deleted, other constitutive elements can be added, and the order can be changed .
Fig. 2 is a flowchart illustrating a method for initializing an image forming apparatus, in accordance with one embodiment of the present disclosure.
According to the imager initialization method, as illustrated in Fig. 2, when power is applied to the system, the main CPU reset is activated by the control logic inside the ASIC (S301), and the reset of the Secondary CPU is not released to be stopped. The reason why the main and secondary CPUs are designed as above is as follows. Generally, if the CPU restore is released, the CPU jumps to a place called the restore vector, in which case the two CPUs execute code in the same place on a bus. In this case, a different type of CPU executes code, and in case you use code that is not compatible, even if the CPU is of the same series (eg ARM), initialization may be impossible. Otherwise, restore vectors for the two CPUs can be defined separately (in the case of ARM, 0x0 or OxffffOOOO), and a method that uses the ROMs, respectively, can be used. In this case, however, a separate memory is additionally required. Also, if multiple CPUs go into an ASIC, most of the hardware can be shared and, in such a system, a complicated synchronization, such as which CPU is initialized and when execution is complete, must be performed. Accordingly, in the present disclosure, when power is applied to the system, the secondary CPU reset is not released, and the main CPU finishes the H/W initialization, and releases the secondary CPU reset to simplify the boot process. then, if the restore is released, the main CPU executes code in the restore vector. For example, the main CPU performs the H/W initialization process, for example, like executing CPU initialization, PLL setting (clock), and DDR setting (S205). completed, it becomes possible When accessing thisDRAM. process forThe main CPU then copies the program code, which the secondary CPU must execute in the DRAM (S210). In this case, a typical AMP system (a system in which this type of CPU shares a bus) can divide and use the DRAM area.
Then the setting of the address change by the ATU is performed (S215). The reason will be described simply. Generally, in the case where secondary CPU restore is enabled, the restore vector code is executed. As illustrated in Fig. 3, the code is accessed with address 0x0. However, in the case of accessing address 0x0 in its state, the address may overlap with the restore address of an area that the main operating system uses to cause a malfunction to occur. To avoid this, a predefined address range is defined, and if the secondary CPU's access address is included in the defined address range, the ATU performs the function of changing the address to the specified address. In the embodiment, as illustrated in Fig. 3, addresses from 0x0 to Oxff are defined in the predefined address area, and if the secondary CPU access address is included in the corresponding address area, the address is changed to address 0x100000000 , to perform the corresponding operation.
Then, the main CPU releases the backup from the secondary CPU, using process control unit 255 (S220).
The main CPU copies the main program (OS) to DDR memory (S225) and proceeds with the initialization process such as main program initialization or similar (S230). Then the main CPU is changed to an operating state (S235) . Here, it is also possible to proceed with operations S210, S215 and S220 after the main program (SO) initialization operation (S230).
On the other hand, the secondary CPU runs the restore vector and subsequent process according to the restore release operation. Specifically, the secondary CPU can perform a hardware initialization task such as subprogram initialization (S240) (eg realtime OS). In addition, the secondary CPU can send a "prep ready" signal to the main CPU using the inter-controller communication unit 160 (S245). Thereafter, the secondary CPU is changed to an operating state (S250). However, operation S245 can be omitted, depending on the circumstances.
Fig. 4 is a diagram illustrating the configuration of a communication unit between controllers 160 implemented by a message queue, which is implemented by FIFO in the ASIC. If the main CPU writes a message to FIFO, an interrupt occurs in the secondary CPU, and the secondary CPU 5 confirms the corresponding message through a FIFO read operation. This is exemplary, and the controller-to-controller communication unit 160 can be implemented in various methods such as Uart, simple IRQ generation, and the like.
Fig. 5 is a flowchart illustrating a method for controlling an image forming apparatus in accordance with one embodiment of the present disclosure.
In the method for controlling an image forming apparatus as illustrated in Fig. 5, it is assumed that the secondary CPU has a low power service code.
According to the method, as illustrated in Fig.5, if a predefined low power change condition is satisfied ("Y" in S410) in a general operating state (S405), the main controller prepares a low state. energy (S415) . Here, the general working state can be a task performer state, like print/scan, or the like, and the default low power mode change condition can be a case, where an idle time is maintained for a preset time. , or more, after the completion of the task.
In operation S415, the secondary controller 120 assembles microcode, or the like, to perform a low-power mode service in the second memory 125 for the low-power service, and performs various types of pre-tasks to change the low-power mode. , such as controller backup interrupt and service stop, main timer stop, and the like.
Upon completion of the low power mode state preparation task, the main controller backs up its context information held in context storage unit 145 (S420).
After that, the master controller requests the slave controller (S425) to change the low power mode. On the other hand, since cache information from the main controller is also lost, when the power is turned on, the cache data is reflected by the cache stream into the DRAM.
In S425 operation, the primary controller reports the start of low power service to the secondary controller, and waits for the power to switch.
The secondary controller changes the mode to low power service mode if it receives the low power service request from the primary controller in S425 operation.
Specifically, if the slave controller receives the request to perform low power service ("Y" in S435) in the general operating state (S430), it copies a low power service program into the second memory 125, which is accessible when the DRAM is turned off (S440).
In addition, the secondary controller sets the ATU to execute it in a second memory location 125 when the interrupt occurs (S445). Thereafter, the secondary controller performs the low power service by changing the program counter to the second memory location 125, such as the program executing position (S450).
Then, for low power mode, the secondary controller performs tasks such as changing clock speed, changing network connection speed, and setting H/W for low power service.
Then, the secondary controller changes the first memory 115 to the auto-update state to operate with a standby power of 1W or less (S455).
Thereafter, the secondary controller enters the service state of low power service operation with standby power of 1W or less (S465) by switching the power so that the power of the first power domain PD1 is changed before the operating state of the low power service (S460) .
On the other hand, the low power service mode in an example used in the present disclosure can be implemented as follows.
1. The first memory 115, ie the DRAM, is switched to auto-update mode, the main controller power is intercepted, or the clock is stopped, and only lOpin, which is required in the wake-up event, is activated (Wake up event can include various sources, such as job reception over a network, fax reception, USB print request, click a user button, click UI panel, and the like ).
2. Switching power and clock shutdown on SoC and board
3. . The bus operating speed and CPU operating speed are changed to the minimum speeds (up to the bearable service speed. For example, in the case of a USB device, normal operation is performed at 30 MHz or more. At present embodiment, the operating speed of the secondary CPU is lowered to 30 MHz, and the operating speed of the internal bus is lowered to 30 MHz).
4. Main CPU power switch
5. Changing the network operating speed (link speed is reduced from 1GHz to 10MHz. In case of supporting an EEE (Ethernet Energy Efficient) function, the link speed is changed automatically).
6. The mode is changed so that the CPU can use the internal memory, which was used to perform the printing function inside the SoC, in the low power mode state.
7. L2 cache controller is disabled for additional low power state.
Fig. 6 is a flowchart illustrating a method for controlling an image forming apparatus in accordance with another embodiment of the present disclosure.
In the method for controlling the imager apparatus as shown in Fig. 6, as opposed to the method as shown in Fig. 5, it is assumed that the main CPU manages the low power service code.
In the case, where the main CPU manages the low power service code, a method can be used, in which the main CPU copies the low power service code into the second memory, and restarts the secondary CPU in low service mode. power, using the process control unit 155, rather than a method, in which the main CPU requests the low-power service change from the secondary CPU, and the secondary CPU copies the low-power code into the second memory (Fig. 5).
According to the method for controlling the imager apparatus as illustrated in Fig. 6, if the preset mode switching condition is satisfied ("Y" in S510) in a general operating state (S505), the main CPU prepares the low power mode state (S515). In this case, the main CPU inquires the secondary CPU if the low power state is possible, and if a response is received, which indicates that the low power state is possible, the main CPU can send a mode change command. low power to the secondary CPU. The secondary CPU is changed to a state, where the CPU no longer works, when the change command is received. Specifically, the secondary CPU is changed to a state where the secondary CPU does not send any requests out. For example, in the case of ARM, interrupt reception is stopped, and the state is changed to a WFI mode.
Then the main CPU stores the execution context information, which should be done in backup mode, when the first power domain PD1 is turned off (S520).
In addition, the main CPU copies the low power service program, which must be activated when the secondary CPU is reset in second memory 125 (S525).
Then the primary controller sets the ATU so that the secondary controller is activated in second memory 125 when reset is activated (S530). Here, the order of operations S525 and S53 0 can be changed between
After that, the main CPU resets the secondary CPU, using the process control unit 155 (S535) .
Once the restore has been performed, the secondary CPU restarts from the sleep vector (S545) . At this time, since the ATU is changed to the second memory 125 by the main controller, the secondary CPU executes a code from the second memory 125, that is, the low power service code.
Then, for low power mode, the secondary CPU performs clock speed change, network connection speed change, and H/W setting for low power service (S550) .
Then, the secondary CPU changes the first memory 115 to the auto-update state to operate with standby power of 1W or less.
Thereafter, the secondary CPU enters the low power service operating state, with standby power of 1W or less (S560), switching power, so that the power of the first power domain PD1 is switched before the operating state of the low power service (S555). Fig. 7 is a flowchart illustrating a process of restoring the low power mode to a normal mode, disclosure.
According to the reset process as illustrated in Fig. 7, if there is a request to change the normal mode ("Y" in S610) into a low power service operating state (S605), the secondary controller takes over the procedure for restoring the imager service mode.
First, in order for the primary controller to determine low power mode initialization, rather than normal initialization during restore, the secondary controller assigns the low power mode initialization data to the initialization mode determining unit 150 (S615 ). However, it is possible to run the job in S615 operation, even in the low power mode entry process, which is not the restore process.
Then, the secondary controller applies power to the first power domain to initialize the main controller (S620), and releases the rest of the main CPU through process control unit 155 (S625). Therefore, the master controller performs initialization. On the other hand, in a system where reset is automatically activated, when the main controller applies power to it, the S620 and S625 operations can be integrated into a single operation.
The CPU can be reset, after the mode is changed from low power mode to normal mode, before main CPU reset is activated in S625 operation, and in case of low power boot mode, the main CPU can change the mode to normal mode, before S630 operation. Here, normal mode means that first memory 115 exits auto-update mode, CPU and internal bus operating speeds are restored to normal mode speed, and other internal hardware is changed to a state, where the task processing is possible. However, according to the system, the clock and power can be applied to a part of the system only during task processing, and the part that is not needed in task processing can, in addition, support the functions of power off and clock switching.
If the main CPU is initialized by the secondary CPU, the main CPU determines the boot mode through the boot mode determination unit 150 (S630).
If general boot mode is determined in S630 operation, the service is performed (S650) through general system boot procedures such as setting clock/DRAM (S635), setting and triggering H/W (S640), and OS loading and triggering (S645).
If low power startup mode is determined in S53 0 operation, since the DRAM is not in a power off state but is in an auto-update mode, it simply exits the auto-update mode. By doing so, the main CPU is in a DRAM-accessible state, and all information before going into low-power mode is contained in the DRAM. However, the CPU context, ie the registration information and the status register are lost and thus the restoration to the previous state is not directly performed. Therefore, the main controller restores the information stored in the context storage unit 145 (S655). As described above, the registers for respective modes are all reset, and the value of "PC" is finally moved to the previous execution point, to restore the service-doing state, before entering the low power mode.
Here, minimum H/W registers, except for the information that is lost, when the power supply to the CPU context core is cut, can be added to the context information, and since the DRAM is in the state of automatic update, the storage and restore time can be several hundred seconds or less, just like storing information in an area of SRAM or DRAM within the SoC.
Fig. 8 is a flowchart illustrating a method for controlling an image forming apparatus, in accordance with one embodiment of the present disclosure.
The image forming apparatus, which is applied to the method for controlling the image forming apparatus of Fig. 8, may include first and second memories, a main controller for performing a control operation using the first memory in a normal mode state, a secondary controller mounted on the drive unit to perform an image forming task by driving the drive unit in the normal mode state under the control of the main controller, a communication unit between controllers relaying communication between the main controller and the secondary controller, and a change of address unit defining a memory address to be accessed by the secondary controller in the low power mode state.
According to the method for controlling the image forming apparatus as shown in Fig. 8, if the condition for changing the mode state from the normal mode state to the low power mode state is satisfied, the main controller transmits a low power mode change request to the secondary controller (S710).
Then, if the low power mode change request is received, the secondary controller copies the low power service program stored in the first memory to the second memory and controls the change address unit to set the memory address. to be accessed in the second memory (S720).
After that, the secondary controller performs the low power service by executing the low power service program by accessing the memory address defined by the change address unit (S730). Here, the main controller and the secondary controller are arranged in different power domains, and the method for controlling the imaging apparatus may further include the secondary controller, intercepting the power, which is supplied to the power domain, in which the main controller is arranged, if the low power mode In addition, if the imager is turned on, power can be supplied to the respective power domains, in which the main controller and the secondary controller are arranged. Furthermore, if the imager is turned on and power is supplied, the main controller assumes a reset release state to perform initialization, sets the access address through the control of the change address unit, it transmits a reset release signal to the secondary controller and then operates in the normal mode state, starting the main program, after transmitting the reset release signal to the secondary controller.25 In addition, the secondary controller maintains the reset state, until the reset release signal is received, after the imager is turned on, and if the reset release signal is received, the secondary controller assumes the reset release state to operate in the normal mode state.
Fig. 9 is a flowchart illustrating a method for controlling an image forming apparatus, in accordance with another embodiment of the present disclosure.
The image forming apparatus, which is applied to the method for controlling the image forming apparatus as illustrated in Fig. 9, may include first and second memories, a main controller for performing a control operation using the first memory in a state normally, a secondary controller mounted on the drive unit to perform an imaging task, by driving the drive unit in the normal mode state under the control of the main controller, and performing a low power service in a low power state, a controller-to-controller communication unit relaying communication between the primary controller and the secondary controller, and a change-of-address unit defining a memory address to be accessed by the secondary controller in the low power state.
According to the method for controlling the image forming apparatus as illustrated in Fig. 8, if the condition for changing the mode state from the normal mode state to the low power mode state is satisfied, the main controller copies the low power service program is stored in the first memory, to the second memory, and transmits the reset signal to the secondary controller (8810).
Then, if the reset signal is received, the secondary controller performs the low power service by executing the low power service program by accessing the second memory according to the memory address set by the changeover unit. address (S820).
In addition, the primary controller and the slave controller are arranged in different power domains and if low power mode is executed, the slave controller intercepts the power, which is supplied to the power domain, in which the primary controller is arranged. .
In addition, the image forming apparatus further includes a power supply unit supplying power to the respective power domains, in which the main controller and the slave controller are arranged, if the image forming apparatus is turned on, and if the image forming apparatus. images is turned on and power is supplied, the main controller assumes the reset release state to perform initialization, sets the access address through the change address unit control, transmits the reset release signal to the secondary controller and then it operates in the normal mode state by starting the main program, after transmitting the reset release signal to the secondary controller.
In addition, the secondary controller maintains the reset state, until the reset release signal is received after the imager is turned on, and if the reset release signal is received, the secondary controller assumes the state of reset release to operate in normal mode state.
Fig. 10 is a flowchart illustrating a method for controlling an image forming apparatus according to yet another embodiment of the present disclosure. The image forming apparatus which is applied to the method for controlling the image forming apparatus , may include a drive unit performing an imaging task, a secondary controller 20 mounted on the drive unit to perform the imaging task, and a main controller controlling the operation of the drive unit by communicating with a drive unit controller in a normal mode and being inactivated if the imager changes a mode to a low energy mode.
According to the method for controlling the image forming apparatus as illustrated in Fig. 10, the driver of the drive unit performs the image forming task by driving the drive unit in normal mode under the control of the main controller (S910).
Then, if the imager changes the mode to low power mode, the drive unit controller provides a service that corresponds to the low power mode (S920).
Here, the imager can further include first and second memories, and an address change unit defining a memory address to be accessed by the secondary controller in the low power state, and the main controller can perform the control operation using the first memory in the normal mode state.
In addition, if the imager changes the mode to low power mode, the secondary controller sets the memory address to be accessed in the second memory under the control of the secondary controller, or the primary controller.
In addition, the primary controller and the slave controller are arranged in different power domains, and if low power mode is executed, the slave controller intercepts the power, which is supplied to the power domain, in which the primary controller is arranged. ,
In addition, the secondary controller performs at least one of first memory auto-update mode change, clock speed change to low power mode, network connection speed change, and a hardware setting (H/W ) for low power mode service, when the mode is changed from normal mode to low power mode.
In addition, the present disclosure may include a computer-readable, permanent recording media that includes a program for performing the method of controlling the image forming apparatus, as described above. Computer-readable recording media includes all kinds of permanent recording devices, on which data, which can be read by a computer, is stored in the system. Examples of computer readable, permanent recording media may include a ROM, RAM, CD-ROM, magnetic tape, floppy disk and optical data storage device, and computer readable recording media can store and play codes, which are distributed on the computer system, which is connected to a network, and can be read by a computer in a distribution method.
Furthermore, the embodiments of the present disclosure can be applied to various communication methods, eg communication network, USB, Bluetooth, HDMA (High Definition Multimedia Interface), PCI (Peripheral Component Interconnect) Express, Ethernet, ZigBee, FireWire , CAN, IEEE 1394, PS/2, AGP (Accelerated Graphics Port), ISA (Industry Standard Architecture), MCA (Micro Channel Architecture), EISA (Extended Industry Standard Architecture), VESA (Video Electronics Standard Architecture), and the like.
On the other hand, the image forming apparatus is exemplified in the embodiments described above. However, this is merely exemplary, and the same principle and definition can be applied to other electronic devices, so that the technical concept, according to the present disclosure, can be applied.
As described above, according to the present disclosure, a CPU is used for real-time service in normal mode, and is used for low-power service in low-power mode, and thus the number of port counters of the ASIC can be reduced to improve cost competitiveness. That is, the secondary controller (or secondary CPU), which has been used to control the drive/scan/fax unit in normal mode, can be used for low power service. Furthermore, the AMP system, which is implemented in a complicated way using MMU software or a special technique, can simply be implemented using the ATU.
Although the disclosure has been shown and described with reference to certain embodiments, it should be clear to those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as defined by the appended claims. .

权利要求:
Claims (15)
[0001]
1. IMAGE MAKING APPARATUS (100), characterized by the fact that it comprises: first and second memories (115, 125); and a main controller (110) and a slave controller (120); where the main controller (110) performs a control operation using the first memory (115) in a normal mode state, the slave controller (120) is mounted in a unit driver (140) provided in the image forming apparatus (100) to perform an image forming task by driving the driver unit (140) in a normal mode state under the control of the main controller (110), the main controller (110) transmits a low power mode change request to the secondary controller (120) if a condition for changing a mode state from the normal mode state to a low power mode state is satisfied, and the secondary controller (120 ) copies a low-power service program stored in the first memory (115) to the second memory (125), if the low-power mode change request is received, and performs a low-power service by executing the low energy service program, through access to the second memory (125).
[0002]
2. IMAGE MAKING APPARATUS (100), according to claim 1, characterized in that it further comprises: communication unit between controllers (160), relaying communication between the main controller (110) and the secondary controller (120); and change address unit (165) defining a memory address to be accessed by the secondary controller (120) in the low power state; where the secondary controller (120) controls the change address unit (165) to set the address of memory to be accessed in the second memory (125), and performs the low-power service, executing the low-power service program by accessing the second memory, in accordance with the defined memory address.
[0003]
3. IMAGE MAKING APPARATUS (100), according to claim 1 or 2, characterized in that the main controller (110) and the secondary controller (120) are arranged in different power domains, and if the low power mode is accomplished, the secondary controller (120) intercepts the power, which is supplied to the power domain, in which the main controller (110) is disposed.
[0004]
4. IMAGE MAKING APPARATUS (100), according to any one of claims 1 to 3, characterized in that it further comprises a power supply unit (130) providing power to respective power domains, in which the main controller ( 110) and the secondary controller (120) are arranged, if the image forming apparatus (100) is turned on; wherein, if the image forming apparatus (100) is turned on and power is supplied, the main controller (110) assumes a reset release state to perform initialization, sets the access address, by controlling the change address unit (165), transmits a reset release signal to the secondary controller (120), and then , operates in the normal mode state, initializing a main program, and the secondary controller (120) maintains a reset state, until the reset release signal is received, after the imager (100) is read. enabled, and assumes the reset release state to operate in the normal mode state, if the reset release signal is received.
[0005]
5. IMAGE MAKING APPARATUS (100), characterized by the fact that it comprises: first and second memories (115, 125); and main controller (110) and secondary controller (120); where the main controller (110) performs a control operation, using the first memory (115) in a normal mode state, the secondary controller (120) is mounted on a unit driver (140) provided in the image forming apparatus (100) to perform an image forming task by driving the driver unit (140) in a normal mode state under the control of the main controller (110) and to perform a service In a low power mode state, the main controller (110) copies a low power service program stored in the first memory (115) to the second memory (125), and transmits a reset signal to the controller. secondary (120), if a condition for changing a mode state from the normal mode state to a low power mode state is satisfied, and the secondary controller (120) performs the low power service by executing the program. low power service, via access to the second memory (125), if the reset signal is received.
[0006]
6. IMAGE MAKING APPARATUS (100), according to claim 5, characterized in that it further comprises: communication unit between controllers (160) relaying communication between the main controller (110) and the secondary controller (120); and change address unit (165) defining a memory address to be accessed by the secondary controller (120) in the low power state; where the main controller (110) controls the change address unit (165) to set the address of memory to be accessed in the second memory (125), and the secondary controller (120) performs the low power service, executing the low power service program, through accessing the second memory (125), according to the address of memory set, if the reset signal is received.
[0007]
7. IMAGE MAKING APPARATUS (100), according to claim 5 or 6, characterized in that the main controller (110) and the secondary controller (120) are arranged in different power domains, and if the low power mode is accomplished, the secondary controller (120) intercepts the power, which is supplied to the power domain, in which the primary controller (110) is disposed.
[0008]
8. IMAGE MAKING APPARATUS (100), according to any one of claims 5 to 7, characterized in that it further comprises a power supply unit (130) providing power to respective power domains, in which the main controller ( 110) and the secondary controller (120) are arranged, if the image forming apparatus (100) is on; wherein, if the imager (100) is turned on and power is supplied, the main controller (110) assumes a reset release state to perform initialization, sets the access address by controlling the unit. address change (165), transmits a reset release signal to the secondary controller (120) and then operates in the normal mode state, starting a main program, and the secondary controller (120) maintains a reset state until that the reset release signal is received, after the imager (100) is turned on, and assume the reset release state to operate in the normal mode state, if the reset release signal is received.
[0009]
9. METHOD FOR CONTROLLING AN IMAGE MAKING APPARATUS (100), characterized in that it includes first and second memories (115, 125), a main controller (110) performing a control operation, using the first memory (115) in a normal mode state, and a secondary controller (120) mounted on the driver unit (140) to perform an imaging task by driving the driver unit (140) in the normal mode state under the control of the main controller (110), and in that the method further comprises: the main controller (110) transmits a low power mode change request to the secondary controller (120) if a condition for changing a mode state, from the normal mode state to a state. of low power mode, is satisfied; the secondary controller (120) copies a low power service program, stored in the first memory (115), to the second memory (125), if the request to change the low power mode ia is received; and the secondary controller (120) provides a low power service by executing the low power service program by accessing the second memory (125).
[0010]
10. METHOD FOR CONTROLLING AN IMAGE MAKING APPARATUS (100), according to claim 9, characterized in that the image forming apparatus (100) further includes a communication unit between controllers (160) relaying communication between the main controller (110) and the secondary controller (120) and an address change unit (165) defining a memory address to be accessed by the secondary controller (120) in the low power state; The method for controlling the image forming apparatus (100) further comprises the secondary controller (120) controlling the address change unit (165) to set the memory address to be accessed in the second memory (125); performing the low power service performs the low power service by executing the low power service program by accessing the second memory (125) in accordance with the defined memory address.
[0011]
11. METHOD FOR CONTROLLING AN IMAGE MAKING APPARATUS (100), according to claim 9 or 10, characterized in that the main controller (110) and the secondary controller (120) are arranged in different energy domains; and of the method for controlling an imager (100) further comprising the secondary controller (120) intercepting power, which is supplied to the power domain, in which the main controller (110) is disposed, if the low power mode is accomplished.
[0012]
12. METHOD FOR CONTROLLING AN IMAGE MAKING APPARATUS (100), according to any one of claims 9 to 11, characterized in that it further comprises: supply of energy for respective energy domains, in which the main controller (110) and the secondary controller (120) are arranged, if the image forming apparatus (100) is turned on; if the image forming apparatus (100) is turned on and power is supplied, the main controller (110) assumes a release state of reset to perform initialization, sets the access address, by controlling the change address unit (165), transmits a reset release signal to the secondary controller (120) and then operates in the normal mode state , by starting a main program after transmitting the reset release signal to the secondary controller (120); and the secondary controller (120) maintains a reset state, until the reset release signal is received, after the imager (100) is turned on, and if the reset release signal is received, it assumes the state of reset release to operate in normal mode state.
[0013]
13. METHOD FOR CONTROLLING AN IMAGE MAKING APPARATUS (100), characterized in that it includes first and second memories (115, 125), a main controller (110) performing a control operation, using the first memory (115) in a normal mode state, and a secondary controller (120) mounted on the driver unit to perform an imaging task, by driving the driver unit (140) in the normal mode state under the control of the main controller (110) and to perform a low power service in a low power state, and in that the method comprises: the main controller (110) copying a low power service program stored in the first memory (115) to the second memory (125) and transmitting a reset signal to the secondary controller (120) if a condition for changing a mode state from the normal mode state to a low power mode state is satisfied; and the secondary controller (120) provides the low power service by executing the low power service program by accessing the second memory (125) if the reset signal is received.
[0014]
14. METHOD FOR CONTROLLING AN IMAGE MAKING APPARATUS (100), according to claim 13, characterized in that the image forming apparatus (100) further includes a communication unit between controllers (160) relaying communication between the main controller ( 110) and the secondary controller (120) and an address change unit (165) defining a memory address to be accessed by the secondary controller (120) in the low power state; The method for controlling the imager apparatus (100) further comprises The main controller (110) operative to set the memory address to be accessed in the second memory (125); where the step of performing the low energy service performs the service low power, executing the low power service program by accessing the second memory (125) in accordance with the defined memory address.
[0015]
15. METHOD FOR CONTROLLING AN IMAGE MAKING APPARATUS (100), according to claim 13 or 14, characterized in that the main controller (110) and the secondary controller (120) are arranged in different energy domains, and the method for controlling an image forming apparatus (100) further comprising the secondary controller (120) intercepting power, which is supplied to the power domain, in which the main controller (110) is disposed, if the low power mode is performed.

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同族专利:

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公开号 | 公开日

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AU2012251164B2|2016-11-03|

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AU2012251164A1|2013-10-17|

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US9451112B2|2016-09-20|

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KR20120124776A|2012-11-14|

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EP2521345A3|2016-12-21|

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ZA201308772B|2014-08-27|

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US20120284550A1|2012-11-08|

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US20150098102A1|2015-04-09|

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JP2012232589A|2012-11-29|

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EP2521345B1|2019-11-27|

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RU2013153584A|2015-06-10|

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RU2592415C2|2016-07-20|

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WO2012150847A3|2013-03-21|

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CA2834842A1|2012-11-08|

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KR101766835B1|2017-08-09|

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WO2012150847A2|2012-11-08|

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TWI558161B|2016-11-11|

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BR112013025855A2|2016-12-20|

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TW201306553A|2013-02-01|

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EP2521345B8|2020-01-01|

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CN102883086A|2013-01-16|

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EP2521345A2|2012-11-07|

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CN102883086B|2018-05-18|

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US9015506B2|2015-04-21|

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法律状态:
2017-05-30| B25A| Requested transfer of rights approved|Owner name: S-PRINTING SOLUTION CO., LTD. (KR) |

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2018-12-04| B25D| Requested change of name of applicant approved|Owner name: HP PRINTING KOREA CO., LTD. (KR) |

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2018-12-11| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|

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2019-10-22| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|

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2019-12-03| B25A| Requested transfer of rights approved|Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (US) |

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2021-03-16| B07A| Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]|

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2021-07-27| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|

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2021-08-24| B16A| Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 04/05/2012, OBSERVADAS AS CONDICOES LEGAIS. |

优先权:

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申请号 | 申请日 | 专利标题

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